| Title |
Area-Delay and Power-Efficient Braun Multiplier Based on GDI (Gate Diffusion Input) |
| Abstract |
Multipliers are essential components in modern digital devices, but multiplication operations are costly and can slow down overall performance. Since multipliers are complex circuits that must operate at high system clock rates, minimizing their delay is crucial for optimizing the overall design. Today, reducing the delay, area, and power consumption of multiplier circuits is key to enhancing the efficiency of the entire system, advancing technology to new heights. To meet the demands of current digital devices, various low-power and high-performance multipliers have been developed. High-performance multipliers are preferred to meet these requirements. The proposed technique offers reduced power dissipation and lower propagation delay. By utilizing this GDI-based multiplier, the number of transistors required is minimized, leading to a more efficient multiplier design. |
| Keywords |
Multipliers, digital devices, power dissipation, propagation delay, GDI, low power, high performance, transistor minimization |
| Research Area |
Engineering |
| Research Paper |
|
| Author(s) |
Vijay Prakash, Swapnali Nagre |
| Country |
India |
